1. Field of the Invention
This invention relates generally to the structure and fabrication of alignment marks on semiconductor chips and more particularly to the fabrication of alignment marks for a process using trench isolation and chemical mechanical polishing.
2. Description of the Prior Art
The fabrication of microcircuit devices on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic masks on the wafer. The masking step includes an etching step and defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition and impurity introduction.
In the production of integrate circuit structures, it has become increasingly important to provide structures having a plurality of metallization layers due the ever increasing density of the circuit elements in the structure. Further, as the device and feature sizes becoming smaller, it is important that the photolithographic mask be aligned precisely with the wafer during the masking step to minimized the misalignment between the layers. Most alignment schemes require the use of alignment targets that were defined on the wafers in the previous layer. One such scheme involves the use of two alignment targets that were defined on the wafer subsequent layers being aligned with respect to these two alignment targets. Typically, each alignment target comprises topographical marks which can be formed by etching into the wafer a plurality of steps with a height of, for example 1200 .ANG. and a width and spacing between each step of, for example 10 .mu.m. The alignment targets are used to diffract a laser alignment beam generated by a photolithography machine commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative position of the wafer and the photolithographic mask is adjusted accordingly so that the pattern for the photolithographic mask are transferred to the wafer in the precise location as desired.
During the fabrication of the integrated circuit structures, a number of metallization layers are formed. Each of the metallization layer is typically separated from another metallization by an insulating layer. To provide an overlying metallization layer without discontinuities or other flaws, it is desirous to provide an underlying surface for the metallization layer that is as flat or planar as possible. It has therefore, become the practice to smooth the surface of a layer in preparation for a subsequently applied metallization layer by a process of planarization.
Conventional planarization techniques, such as plasma etching or reactive ion etch (RIE) of oxide with a resist planarizing medium, are used to provide a smooth surface and a local planarization with a range of typically less then 1 .mu.m. Smoothing is achieved over a greater range, but the step topography of the alignment targets is preserved since its step spacing is much greater than the planarization range.
However, to meet the demand for more metal and insulating layers in devices and the stringent depth of focus requirement for submicron lithography, a new planarization technique, commonly known as chemical-mechanical polishing (CMP) is used. U.S. Pat. No. 4,944,836, entitled "Chem-Mech Polishing Method of for Producing Coplanar Metal/Insulator film on a Substrate" issued Jul. 31, 1990 to Beyer et al. discloses one such CMP technique. Typically, CMP planarization of the wafer involves holding the wafer against a rotating polishing pad wet with a silica--based alkaline slurry and at the same time applying pressure. Unlike the conventional planarization techniques, the CMP planarization technique provides a global planarization, that is, one that provide a large planarization range the generally covers the whole wafer surface. Since the planarization range is large, the steps of the alignment targets on a new overlying layer on the wafer will be flattened after it is planarized by a the CMP technique. The steps of the alignment targets on the previous layer are not replicated to the overlying layer. The overlying layer will cause alignment target reading problems by interfering with the diffraction pattern, especially where the overlying layer is a thick oxide or a nitride layer. The problem is even worse with when the newly formed overlying layer is highly reflective or opaque.
New isolation processes, such as shallow trench isolation (STI) create a thick oxide layer over the alignment marks and create the readability problems described above. In the STI process, a silicon nitride layer is formed on a wafer and patterned to have openings where trenches will be formed. Trenches are etched in the substrate. A thick oxide layer is deposited in the trenches and over wafer surface. Next, the thick oxide layer is polished (CMP) to create a planar surface. The CMP process leaves a thick oxide layer over the alignment marks that interferes with the alignment mark reader. FIG. 1A shows a conventional alignment mark trench 24 in an alignment mark area 30 (or alignment mark) having the thick insulating layer 22 over the nitride layer 20 and pad oxide layer 11. As can be seen, after the CMP, the insulating layer covers the alignment marks and does not replicate the alignment mark topography. In the unattractive conventional methods, the oxide layer can be removed by the a photo etch process called a window mask (described below). Another non-optimum alternative is to over polish the wafer, thus removing most of the thick oxide over the alignment marks, but at the same time the over polishing removes oxide from the trenches, thus creating isolation and yield problems.
To overcome the problem of non-readable alignment marks where an oxide or other layer covers the alignment marks, the alignment marks can by uncovered by using a process commonly known as a "window mask" process. Performed after CMP planarization and before contact masking, in the window mask process the alignment marks are exposed and the rest of the wafer is covered by a photoresist layer. The layers over the alignment marks are etched away using the window mask as an etch barrier. This way the alignment marks are not covered and clear. Also, metal layer or other opaque layers can be formed over the alignment marks where the metal layers replicate the alignment mark topography. Accordingly, the wafer stepper can now perform alignment between a photolithographic mask and the wafer in the new photolithographic process. However, the additional window mask and etch steps plus the attendant cleaning and inspections, undesirably increase cycle time and process complexity and also introduce particles and defects, resulting in an increase in cost and yield loss. Hence there is a need to provide a method of removing layers from over alignment marks after a CMP planarization process while at the same time eliminating the window mask and etch steps. The present invention addresses such a need.
Other practitioners have proposed solutions to the non-readable alignment mark problem. U.S. Pat. No. 5,456,756 (Ramaswami) preserves alignment marks using a holding apparatus and method where a clamp covers an alignment mark and prevents material from being deposited over the alignment marks. U.S. Pat. No. 5,275,965 (Manning) shows a method of forming trench isolation using gates sidewalls. However, these methods can be further improved.